sel4/arch/arm/arch/aarch64/
vcpu_reg.rs

1//
2// Copyright 2023, Colias Group, LLC
3// Copyright (c) 2020 Arm Limited
4//
5// SPDX-License-Identifier: MIT
6//
7
8use sel4_config::sel4_cfg_enum;
9
10use crate::sys;
11
12/// Corresponds to `seL4_VCPUReg`.
13#[repr(u64)]
14#[allow(non_camel_case_types)]
15#[sel4_cfg_enum]
16pub enum VCpuReg {
17    SCTLR = sys::seL4_VCPUReg::seL4_VCPUReg_SCTLR,
18    TTBR0 = sys::seL4_VCPUReg::seL4_VCPUReg_TTBR0,
19    TTBR1 = sys::seL4_VCPUReg::seL4_VCPUReg_TTBR1,
20    TCR = sys::seL4_VCPUReg::seL4_VCPUReg_TCR,
21    MAIR = sys::seL4_VCPUReg::seL4_VCPUReg_MAIR,
22    AMAIR = sys::seL4_VCPUReg::seL4_VCPUReg_AMAIR,
23    CIDR = sys::seL4_VCPUReg::seL4_VCPUReg_CIDR,
24    CPACR = sys::seL4_VCPUReg::seL4_VCPUReg_CPACR,
25    AFSR0 = sys::seL4_VCPUReg::seL4_VCPUReg_AFSR0,
26    AFSR1 = sys::seL4_VCPUReg::seL4_VCPUReg_AFSR1,
27    ESR = sys::seL4_VCPUReg::seL4_VCPUReg_ESR,
28    FAR = sys::seL4_VCPUReg::seL4_VCPUReg_FAR,
29    VBAR = sys::seL4_VCPUReg::seL4_VCPUReg_VBAR,
30    TPIDR_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_TPIDR_EL1,
31    #[sel4_cfg(not(MAX_NUM_NODES = "1"))]
32    VMPIDR_EL2 = sys::seL4_VCPUReg::seL4_VCPUReg_VMPIDR_EL2,
33    SP_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_SP_EL1,
34    ELR_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_ELR_EL1,
35    SPSR_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_SPSR_EL1,
36    CNTV_CTL = sys::seL4_VCPUReg::seL4_VCPUReg_CNTV_CTL,
37    CNTV_CVAL = sys::seL4_VCPUReg::seL4_VCPUReg_CNTV_CVAL,
38    CNTVOFF = sys::seL4_VCPUReg::seL4_VCPUReg_CNTVOFF,
39}
40
41impl VCpuReg {
42    pub const fn into_sys(self) -> sys::seL4_VCPUReg::Type {
43        self as sys::seL4_VCPUReg::Type
44    }
45}
sel4/arch/arm/arch/aarch64/vcpu_reg.rs

sel4/arch/arm/arch/aarch64/
vcpu_reg.rs
