sel4/arch/arm/arch/aarch64/
vcpu_reg.rs

1//
2// Copyright 2023, Colias Group, LLC
3// Copyright (c) 2020 Arm Limited
4//
5// SPDX-License-Identifier: MIT
6//
7
8use sel4_config::sel4_cfg_enum;
9
10use crate::sys;
11
12/// Corresponds to `seL4_VCPUReg`.
13#[repr(u64)]
14#[allow(non_camel_case_types)]
15#[sel4_cfg_enum]
16pub enum VCpuReg {
17    SCTLR = sys::seL4_VCPUReg::seL4_VCPUReg_SCTLR,
18    TTBR0 = sys::seL4_VCPUReg::seL4_VCPUReg_TTBR0,
19    TTBR1 = sys::seL4_VCPUReg::seL4_VCPUReg_TTBR1,
20    TCR = sys::seL4_VCPUReg::seL4_VCPUReg_TCR,
21    MAIR = sys::seL4_VCPUReg::seL4_VCPUReg_MAIR,
22    AMAIR = sys::seL4_VCPUReg::seL4_VCPUReg_AMAIR,
23    CIDR = sys::seL4_VCPUReg::seL4_VCPUReg_CIDR,
24    ACTLR = sys::seL4_VCPUReg::seL4_VCPUReg_ACTLR,
25    CPACR = sys::seL4_VCPUReg::seL4_VCPUReg_CPACR,
26    AFSR0 = sys::seL4_VCPUReg::seL4_VCPUReg_AFSR0,
27    AFSR1 = sys::seL4_VCPUReg::seL4_VCPUReg_AFSR1,
28    ESR = sys::seL4_VCPUReg::seL4_VCPUReg_ESR,
29    FAR = sys::seL4_VCPUReg::seL4_VCPUReg_FAR,
30    ISR = sys::seL4_VCPUReg::seL4_VCPUReg_ISR,
31    VBAR = sys::seL4_VCPUReg::seL4_VCPUReg_VBAR,
32    TPIDR_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_TPIDR_EL1,
33    #[sel4_cfg(not(MAX_NUM_NODES = "1"))]
34    VMPIDR_EL2 = sys::seL4_VCPUReg::seL4_VCPUReg_VMPIDR_EL2,
35    SP_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_SP_EL1,
36    ELR_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_ELR_EL1,
37    SPSR_EL1 = sys::seL4_VCPUReg::seL4_VCPUReg_SPSR_EL1,
38    CNTV_CTL = sys::seL4_VCPUReg::seL4_VCPUReg_CNTV_CTL,
39    CNTV_CVAL = sys::seL4_VCPUReg::seL4_VCPUReg_CNTV_CVAL,
40    CNTVOFF = sys::seL4_VCPUReg::seL4_VCPUReg_CNTVOFF,
41}
42
43impl VCpuReg {
44    pub const fn into_sys(self) -> sys::seL4_VCPUReg::Type {
45        self as sys::seL4_VCPUReg::Type
46    }
47}
sel4/arch/arm/arch/aarch64/vcpu_reg.rs

sel4/arch/arm/arch/aarch64/
vcpu_reg.rs
