sel4/arch/riscv/
invocations.rs

1//
2// Copyright 2023, Colias Group, LLC
3//
4// SPDX-License-Identifier: MIT
5//
6
7use crate::{
8    AbsoluteCPtr, Cap, CapRights, CapTypeForFrameObject, Error, InvocationContext, Result,
9    TranslationTableObjectType, VmAttributes, Word, cap::*, cap_type,
10};
11
12impl<T: CapTypeForFrameObject, C: InvocationContext> Cap<T, C> {
13    /// Corresponds to `seL4_RISCV_Page_Map`.
14    pub fn frame_map(
15        self,
16        page_table: PageTable,
17        vaddr: usize,
18        rights: CapRights,
19        attrs: VmAttributes,
20    ) -> Result<()> {
21        Error::wrap(self.invoke(|cptr, ipc_buffer| {
22            ipc_buffer.inner_mut().seL4_RISCV_Page_Map(
23                cptr.bits(),
24                page_table.bits(),
25                vaddr.try_into().unwrap(),
26                rights.into_inner(),
27                attrs.into_inner(),
28            )
29        }))
30    }
31
32    /// Corresponds to `seL4_RISCV_Page_Unmap`.
33    pub fn frame_unmap(self) -> Result<()> {
34        Error::wrap(
35            self.invoke(|cptr, ipc_buffer| {
36                ipc_buffer.inner_mut().seL4_RISCV_Page_Unmap(cptr.bits())
37            }),
38        )
39    }
40
41    /// Corresponds to `seL4_RISCV_Page_GetAddress`.
42    pub fn frame_get_address(self) -> Result<usize> {
43        let ret = self.invoke(|cptr, ipc_buffer| {
44            ipc_buffer
45                .inner_mut()
46                .seL4_RISCV_Page_GetAddress(cptr.bits())
47        });
48        match Error::from_sys(ret.error) {
49            None => Ok(ret.paddr.try_into().unwrap()),
50            Some(err) => Err(err),
51        }
52    }
53}
54
55impl<C: InvocationContext> PageTable<C> {
56    pub fn page_table_map(self, vspace: PageTable, vaddr: usize, attr: VmAttributes) -> Result<()> {
57        Error::wrap(self.invoke(|cptr, ipc_buffer| {
58            ipc_buffer.inner_mut().seL4_RISCV_PageTable_Map(
59                cptr.bits(),
60                vspace.bits(),
61                vaddr.try_into().unwrap(),
62                attr.into_inner(),
63            )
64        }))
65    }
66}
67
68impl<C: InvocationContext> UnspecifiedIntermediateTranslationTable<C> {
69    pub fn generic_intermediate_translation_table_map(
70        self,
71        ty: TranslationTableObjectType,
72        vspace: VSpace,
73        vaddr: usize,
74        attr: VmAttributes,
75    ) -> Result<()> {
76        match ty {
77            TranslationTableObjectType::PageTable => self
78                .cast::<cap_type::PageTable>()
79                .page_table_map(vspace, vaddr, attr),
80        }
81    }
82}
83
84impl<C: InvocationContext> IrqControl<C> {
85    /// Corresponds to `seL4_IRQControl_GetTrigger`.
86    pub fn irq_control_get_trigger(
87        self,
88        irq: Word,
89        edge_triggered: bool,
90        dst: &AbsoluteCPtr,
91    ) -> Result<()> {
92        Error::wrap(self.invoke(|cptr, ipc_buffer| {
93            ipc_buffer.inner_mut().seL4_IRQControl_GetTrigger(
94                cptr.bits(),
95                irq,
96                edge_triggered.into(),
97                dst.root().bits(),
98                dst.path().bits(),
99                dst.path().depth_for_kernel(),
100            )
101        }))
102    }
103}
104
105impl<C: InvocationContext> AsidControl<C> {
106    /// Corresponds to `seL4_RISCV_ASIDControl_MakePool`.
107    pub fn asid_control_make_pool(self, untyped: Untyped, dst: &AbsoluteCPtr) -> Result<()> {
108        Error::wrap(self.invoke(|cptr, ipc_buffer| {
109            ipc_buffer.inner_mut().seL4_RISCV_ASIDControl_MakePool(
110                cptr.bits(),
111                untyped.bits(),
112                dst.root().bits(),
113                dst.path().bits(),
114                dst.path().depth_for_kernel(),
115            )
116        }))
117    }
118}
119
120impl<C: InvocationContext> AsidPool<C> {
121    /// Corresponds to `seL4_RISCV_ASIDPool_Assign`.
122    pub fn asid_pool_assign(self, vspace: PageTable) -> Result<()> {
123        Error::wrap(self.invoke(|cptr, ipc_buffer| {
124            ipc_buffer
125                .inner_mut()
126                .seL4_RISCV_ASIDPool_Assign(cptr.bits(), vspace.bits())
127        }))
128    }
129}
sel4/arch/riscv/invocations.rs

sel4/arch/riscv/
invocations.rs
